Graphics and central processors may have a storage system with a large near memory (NM) cache, which is relatively fast, and this is in turn backed by far memory (FM), which is inexpensive, but also much slower. In such a hierarchical memory architecture, it is very important to get a hit rate in NM which is as high as possible, because on a miss, a request will be sent to FM, and it will take a relatively long time before the requested data is accessible. For example the near memory may be volatile memory (i.e. dynamic random access memory) mounted on a graphics/central processing unit of system-on-a-chip. The far memory may be non-volatile memory such as flash memory.
At the same time, the processor can compress some of its buffers to a small set of fixed sizes. The compressed cache lines are stored “sparse” (non-contiguously) for quick random access. Currently, since the NM cannot exploit this type of compression, the compressed data in the NM still has the same footprint as uncompressed data in NM. Thus, a substantial portion of NM, which is more expensive, is unused at any instance in time.
Current render cache data compression techniques, e.g., for color, do not reduce the memory footprint of render buffers. Those techniques only reduce the amount of data traffic to and from memory. Compaction is a way of reducing the memory footprint of already compressed data.
Other lossy data compression techniques can reduce footprint, but only at a potentially unbounded loss of quality. For example, a lossily compressed buffer that is read/modify/written repeatedly can deteriorate in quality. Data loss is in many cases not acceptable (e.g., due to API-compatibility, visual artifacts, non-image data).
Compaction is a way of reducing the memory footprint of already compressed data, without introducing any loss. Footprint reduction in NM enables storing more data, before triggering expensive far memory (FM) accesses. Therefore, the apparent capacity of NM is increased, resulting in higher performance, less expensive system-on-a-chip, and reduced power consumption in some embodiments.